With the advance of a semiconductor process and the improvement of a chip function, increasing integrated circuits can be accommodated in a chip. Based on an industrial manufacturing requirement, an integrated circuit applied to a chip is carried in various dies. With the development of the process and for a purpose of a higher functional requirement, a packaging manner in which two or more than two dies are packaged together catches increasing attention in the industry.
Multiple dies packaged in one chip do not independently work. There is a requirement of data interaction between different dies, and a length of a data path has relatively great impact on performance of a chip. Therefore, how to shorten a length of a path of data communication between dies becomes an important topic in the industry. Currently, there is a three dimensional (3D) integrated packaging technology in the industry. As shown in FIG. 1, a carrier n of a chip 100 carriers a wafer-level packaging (hereinafter referred to as WLP) 18. The WLP 18 includes a die 12, a colloid 14 wrapped around the die 12, and a redistribution layer 15 formed on surfaces of the die 12 and the colloid 14. Bumps 17 are disposed at a bottom of the redistribution layer 15. The redistribution layer 15 and the bumps 17 form a signal path between the die 12 and the carrier 11.
The chip 100 further includes a WLP 28 carried on a top of the WLP 18. Similar to the WLP 18, the WLP 28 includes a die 22, a colloid 24, a redistribution layer 25, and bumps 27. A redistribution layer 19 is disposed on the top of the WLP 18, a vertical interconnect path 13 is disposed in the colloid 14 of the WLP 18. The redistribution layer 25 and the bumps 27 that are of the WLP 28. A signal path is established between the WLP 28 and the WLP 18 by using a metal layer in the redistribution layer 25, the bumps 27, a metal layer in the redistribution layer 19 of the WLP 18, a through silicon via 13, and the redistribution layer 15 of the WLP 18.
In the 3D packaging technology, a length of a signal path between two dies can be effectively shortened by means of superposition of two WLPs, but this also causes a new problem. First, superposition of the two WLPs causes a relatively severe dissipation problem; second, a process of a through silicon via is relatively difficult, which causes relatively high process costs.